A processor built for binary matrix computation
Sparsr runs wide bitwise work over long bit vectors, sparse or dense: bitmaps, molecular fingerprints, hypervectors, parity-check matrices. Mainstream CPUs are 32- or 64-bit machines whose widest SIMD extension tops out around 512 bits. On Sparsr, 8,192 bits is the width of the register file and of the instruction set itself, so a whole row is one operand. Develop and test locally for free.
The architecture, stated plainly
Properties of the machine, stated without comparison to anything else.
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8,192
Bits, natively
Wide registers and wide instructions are the point of the machine, not an extension bolted beside a scalar core. The scalar side is a conventional 32-bit RISC core that drives them.
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1
Register per vector
An 8,192-dimensional binary vector is one operand. One instruction covers it, so a kernel skips the tiling, looping, spilling and cross-lane shuffling a 512-bit machine needs.
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Free
To develop and test
The assembler, the runtime and a full software emulator run on your own machine, free. You do not need hardware access to develop for Sparsr.
A whole row of a binary matrix is one operand
An 8,192-bit row of a bitmap, a fingerprint set or a parity-check matrix fits in one Sparsr register, and one instruction operates on every bit of it. A 512-bit SIMD unit needs sixteen chunks and the loop, the tiling and the cross-lane shuffling that go with them.
No baseline instruction set can express that, and what the machine can express in one instruction is the point here rather than how quickly it runs a loop. Density does not enter into it, because a sparse row and a dense row are the same one operand.
From your laptop to custom silicon
Three stages, and only the first is available to everyone today.
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1
Write and test locally
Write kernels in Sparsr assembly, C or C++, assemble them with spasm, and run them against a full software emulator on your own machine. Free, offline, and suitable for automated testing in CI.
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2
Validate on FPGA
Run the same kernel against the RTL on FPGA hardware. Sparsr's FPGA target is AWS EC2 F2, which is where the design is developed and validated. You can run Sparsr there today, in your own AWS account.
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3
Extend the instruction set
Sparsr's instruction set is designed to grow. Where a workload needs a wide primitive that does not exist yet, adding it at 8,192 bits is ordinary roadmap work — and on a per-project basis it can go as far as a path to dedicated silicon.
The SDK, in full
Everything below runs on your own machine today, for free.
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spasm — the assembler
A cross-assembler for Sparsr assembly, built as one native binary. Wide registers and wide instructions are first-class in the syntax.
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C and C++ intrinsics
sparsr_intrinsics.h exposes the wide instruction set to C and C++, so a kernel does not have to be written in assembly to reach the 8,192-bit registers.
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libsparsr_host.so — the runtime
A host library that loads kernels and moves data, dispatching to whichever backend is selected. That selection happens at run time, so host code does not change when the target does.
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Software emulator
A complete emulator for the Sparsr instruction set, running on your own CPU. It runs the whole instruction set rather than stubbing it, so a local test result means something.
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.NET bindings
A managed wrapper over the host runtime, for host applications written in C# rather than C.
Partner with Sparsr
We work with university labs, institutes and grant consortia on custom instruction set extensions and FPGA co-design. We also work with commercial teams whose workloads are dominated by wide bitwise operations.
If your kernel is mostly AND, XOR and population counts over long bit vectors, we would like to hear about it — including if the primitive you need is one Sparsr does not have yet.